1. Field Of The Invention
The present invention relates to integrated circuits. More particularly, the present invention pertains to sense amplifiers circuits for use in memory integrated circuits.
2. The Prior Art
Single-ended sense amplifiers are commonly used in commodity read only memories and programmable read only memories to detect the presence or absence of a programmed memory cell. Two common examples of single-ended sense amplifier commonly in use today are shown in FIGS. 1 and 2. In the circuit of FIG. 1, the single-ended sense amp is simply an inverter. It requires a relatively large input signal (several volts), produced by the memory cell to switch its output between ground and Vdd. This large input swing significantly slows the operation of the memory product in which this circuit is embodied because the weak memory cell current, 10-100 microamps, must drive a large load, typically 5-10 picofarads (due to many memory cells on a common bit line, and many pass devices on a common I/O line). Therefore, this sense amplifier is only suited for slow designs.
The single-ended sense amplifier depicted in FIG. 2 is a current to voltage converter. It passes the cell current through a resistor, synthesized with P-channel Mos device P1, to convert the current into a voltage. The feedback circuitry, P.sub.2, P.sub.3, N.sub.2 and N.sub.3 establishes the voltage bias level of the I/O and bit line. A feedback clamp N.sub.2 holds the bias level of the I/O line when a bit line is initially accessed. Once the bit line bias has stabilized, the clamp is released and sensing begins. The feedback also squares up the output voltage by amplifying the effect of the I/O voltage movement on the V.sub.gs of the N-channel MOS device N.sub.1.
The sense amplifier of FIG. 2 can detect a few hundred millivolts of signal swing, so it is capable of higher speeds than the inverter sense amplifier of FIG. 1. However, the sense amplifier circuit of FIG. 2 still wastes some speed, and suffers from power supply noise sensitivity.
Speed is lost due to the feedback loop, clamp circuit and lowering the noise sensitivity. The feedback loop adds additional stage delays between the I/O signal and the switching of N1, which slows the squaring of the output voltage. The clamp circuit and sense amp trip points are different, so time is wasted while the I/O line moves between them.
Speed is lost also due to the power supply noise sensitivity of the trip point of the sense amplifier. Since the trip point of the feedback circuit is a function of the power supply voltage, variations in the power supply voltage will affect when N1 switches. The clamp circuit will re-establish the I/O and bit line bias levels if Vdd increases, but must rely on the weak cell current to pull the I/O and bit line down if Vdd becomes lower. Both equalization processes slow the sensing process. Thus, while this sense amplifier of FIG. 2 operates with a smaller signal, and is consequently faster than the inverter sense amp depicted in FIG. 1, it still suffers from power supply noise sensitivity and is still relatively slow.